Comparators are used widely in electronics, including in demanding applications such as analog-to-digital converters, clocks, and sensors. Speed, accuracy, and power consumption are often important parameters in comparator design. In many cases, all three parameters need to be optimized at once. The direct current (DC) accuracy of a comparator is often determined by its systematic and random offsets.
Systematic offsets can usually be minimized by gain and topology, but random offsets are often a result of process variations. Process variations can often be minimized by increasing the area of a device, but this also typically increases parasitic capacitances in the device. This often creates a trade-off between speed, power, and accuracy. An alternative to increasing the size of a device is to use offset cancellation or auto-zeroing techniques. This can eliminate the need for large devices and may allow a comparator to be optimized for speed and power consumption without sacrificing accuracy.
Various offset cancellation techniques have been developed and used. However, each of these techniques typically suffers from one or more drawbacks. For example, some techniques use storage capacitors that sample a comparator's offset during times when the comparator is not needed (referred to as “off-time”). These storage capacitors then hold a voltage associated with the offset when the comparator is in use to cancel out the offset. However, storage capacitors often require large areas, create residual offsets due to charge coupling from switches onto the capacitors, and permit leakage of charge from the capacitors.
Other offset cancellation techniques take advantage of the digital output of a comparator and implement a digital offset cancellation scheme. A conventional offset cancellation circuit 100 is shown in FIG. 1. The circuit 100 includes a comparator 102, a latch 104, a counter 106, and a digital-to-analog converter (DAC) 108. During auto-zeroing, a switch 110 is closed to force both inputs of the comparator 102 to the same value. The latch 104 samples the output of the comparator 102, and the counter 106 increments or decrements its output depending on the latched value. The output of the counter 106 is provided to the DAC 108, which generates an analog offset correction signal that is supplied to an analog offset adjust within the comparator 102. This process can continue until the current offset of the comparator 102 is identified and corrected. An auto-zeroing clock controls the operations of various components in the circuit 100 during auto-zeroing.
In this way, the comparator 102 can be zeroed to within one least significant bit of the DAC 108. However, an inherent digital oscillation typically appears when the DAC 108 nears the point at which the comparator 102 has zero offset. When this point is neared or reached, the counter 106 typically bounces back and forth between a slightly positive offset and a slightly negative offset. For some applications, this oscillation may be acceptable. For other applications, such as applications where the comparator's threshold needs to be consistent, this oscillation is often unacceptable. For example, if the comparator 102 is used in a clock circuit, every cycle of the digital oscillation can lead to jitter in the clock frequency or duty cycle.